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Texas Instruments CDCU2A877 Phase-Lock Loop Clock Driver

Texas Instruments CDCU2A877 Phase-Lock Loop Clock Driver is a high-performance, low-jitter, low-skew, zero-delay buffer. It distributes a differential clock input pair (CK, /CK) to 10 differential pairs of clock outputs (Yn, /Yn) and one differential pair of feedback clock outputs (FBOUT, /FBOUT). The clock outputs are controlled by the input clocks (CK, /CK), the feedback clocks (FBIN, /FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT, /FBOUT, are disabled while the internal PLL maintains its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE does not affect Y7, /Y7, as these are free-running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.

When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on. The inputs and the outputs are then enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time. The Texas Instruments CDCU2A877 can track spread spectrum clocking (SSC) for reduced EMI. This device operates from 0°C to 70°C.

Features

  • 1.8V/1.9V Phase-Lock Loop clock driver for Double Data Rate ( DDR II ) applications
  • Spread spectrum clock compatible
  • 125MHz to 410MHz operating frequency
  • 160MHz to 410MHz application frequency
  • ±40ps low jitter (Cycle-Cycle)
  • 35ps low output skew
  • Stabilization time < 6µs
  • Distributes one differential clock input to 10 differential outputs
  • A high-drive version of CDCUA877
  • 52-Ball mBGA (MicroStar Junior™; BGA, 0.65mm pitch)
  • External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the input clocks
  • Meets or exceeds CUA877/CUA878 specification PLL standard for PC2-3200/4300/5300/6400
  • Fail-safe inputs

Logic Diagram

Schematic - Texas Instruments CDCU2A877 Phase-Lock Loop Clock Driver

Related Product

Texas Instruments CDCUA877 Phase-Lock Loop Clock Driver

Device is a high-performance, low-jitter, low-skew, zero-delay buffer.

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Publicado: 2020-12-18 | Actualizado: 2024-10-22