Renesas Electronics RC38x12 FemtoClock®3 Wireless Synchronizers

Renesas Electronics RC38x12 FemtoClock®3 Wireless 3-Channel Ultra-Low Phase Noise Synchronizers and Jitter Attenuators include the RC38312 and RC38112 devices. These devices are ultra-low phase noise radio synchronizers, multi-frequency clock synthesizers, and digitally controlled oscillators (DCOs). RC38x12 delivers exceptional performance for 5G radio units (RU), distribution units (DU), and network switches/routers. Its capability to output clocks with ultra-low in-band phase noise and significantly reduced spurious levels enhances the reliability and efficiency of 4G/5G RF transceivers.

The Renesas Electronics RC38x12 offers a high margin on reference clock jitter, with up to three synchronization domains and four frequency domains, allowing designers to simplify overall PCB designs and providing a single timing solution supporting both synchronization via CPRI or eCPRI and RF clock generation. The devices offer low power dissipation and a smaller area while achieving ultra-low jitter and maintaining ultra-low phase coherence essential for 5G and 5G-A BTS radio unit designs. Providing flexibility, the RC38x12 allows locking to external reference clocks or free-running crystals/oscillators. The devices feature hitless reference switching to ensure uninterrupted service even when switching between redundant timing sources, making it an ideal choice for providing robust, precise timing across telecommunication applications.

Features

Ultra-low phase noise synthesizer with jitter below 25fs RMS, 12kHz to 20MHz with 4MHz HPF
Three independent low-phase noise sync domains
Four independent low-phase noise frequency domains
Support for JESD204B/C
Time sync block with time-to-digital converter (TDC), time-of-day (TOD) counter, and PTP clocks
Twelve clock outputs with independent integer dividers
- 8: LVDS, HCSL (AC-LVPECL) or CML
- 4: LVDS, HCSL (AC-LVPECL) or LVCMOS
Output frequency ranges
- DC to 2.5GHz for CML
- DC to 1GHz for LVDS or HCSL
- DC to 250MHz for LVCMOS

Four differential or single-ended clock inputs
Operates from a 1.8V supply
Clock inputs tolerate 1.8V input when the device is powered off, sinking less than 1mA
DC to 1GHz CLKIN input frequency range
Time Sync TDC supports 1PPS and PP2S inputs
DPLLs comply with ITU-T G.8262 and G.8262.1
DPLL input-to-output phase variation of ≤100ps
DCO frequency resolution of <10-13
9mm × 9mm, 100-BGA package