Volver a Renesas Electronics

Renesas Electronics 9ZML12x3E Clock Buffers

Renesas Electronics 9ZML12x3E Clock Buffers are second-generation enhanced performance DB1200ZL derivatives. These 9ZML12x3E buffers are pin-compatible with 9ZML1232B and offer improved phase jitter performance. The 9ZML12x3E clock buffers fixed external feedback and maintained low drift for critical QPI/UPI applications. Each input channel has software adjustable input-to-output delay to ease transport delay management for complex server topologies. Features include three selectable SMBus addresses, 100MHz Phase-Locked-Loop (PLL) mode, and software-configurable input-to-output delay lines. These 9ZML1233E and 9ZML1253E buffers offer an SMBus write lockout pin for increased device and system security. Typical applications include servers, storage, networking, and Solid State Drives (SSDs).

Features

  • SMBus write lock feature increases system security
  • 2 software-configurable input-to-output delay lines manage
    transport delay for complex topologies
  • LP-HCSL outputs eliminate 24 resistors and save 41mm2
    of an area (1233E)
  • LP-HCSL outputs with 85Ω Zout eliminate 48 resistors and save
    82mm2 of area (1253E)
  • 12 OE# pins hardware control of each output
  • 3 selectable SMBus addresses multiple devices can share
    same SMBus segment
  • Selectable PLL bandwidths minimize jitter peaking in cascaded
    PLL topologies
  • 100MHz PLL mode and UPI support
  • PCIe clocking architectures supported:
    • Common Clocked (CC)
    • Independent Reference (IR) with and without spread spectrum
  • Output features:
    • 12 Low-Power (LP) HCSL output pairs (1233E)
    • 12 Low-Power (LP) HCSL output pairs with 85Ω Zout (1253E)
  • Hardware/SMBus control of PLL bandwidth and bypass change
    mode without a power cycle
  • Spread spectrum compatible tracks spreading input clock for EMI reduction

Specifications

  • < 50ps cycle-to-cycle jitter
  • < 50ps output-to-output skew
  • 0ps default input-to-output delay
  • < 50ps input-to-output delay variation
  • PCIe Gen4 < 0.5ps rms phase jitter
  • UPI > 9.6GB/s < 0.1ps rms phase jitter
  • IF-UPI < 1.0ps rms phase jitter

Block Diagram

Block Diagram - Renesas Electronics 9ZML12x3E Clock Buffers
View Results ( 4 ) Page
N.º de artículo Hoja de datos Descripción Cantidad de Paquete Estándar
9ZML1233EKILF 9ZML1233EKILF Hoja de datos Búfer de reloj 9ZML1233E DB1200ZL MUX DERIV +WRTLK 168
9ZML1253EKILF 9ZML1253EKILF Hoja de datos Búfer de reloj 9ZML1253E DB1200ZL MUX DERIV LITE +WRTLK 168
9ZML1233EKILFT 9ZML1233EKILFT Hoja de datos Búfer de reloj 9ZML1233E DB1200ZL MUX DERIV +WRTLK 2500
9ZML1253EKILFT 9ZML1253EKILFT Hoja de datos Búfer de reloj 9ZML1253E DB1200ZL MUX DERIV LITE +WRTLK 2500
Publicado: 2018-05-28 | Actualizado: 2023-01-23