Volver a ISSI

ISSI IS46LD CMOS LPDDR2 DRAMs

ISSI IS46LD CMOS LPDDR2 DRAMs are 2Gbit/4Gbit organized as 8 banks of 16Meg/32Meg words of 16bits or 8Meg/16Meg words of 32bits. These DRAMs use a 4bit Double Data Rate (DDR) architecture to achieve high-speed operation. The IS46LD CMOS DRAMs feature Deep Power-Down (DPD) mode, a 10MHz to 533MHz clock frequency range, and Partial Array Self Refresh (PASR). These DRAMs include an on-chip temperature sensor to control the self-refresh rate and High Speed Un-terminated Logic (HSUL_12) I/O interface.

Features

  • Low-voltage core and I/O power supplies:
    • VDD2 = 1.14V to 1.30V, VDDCA/VDDQ = 1.14V to 1.30V
    • VDD1 = 1.70V to 1.95V
  • High Speed Un-terminated Logic (HSUL_12) I/O interface
  • 10MHz to 533MHz (data rate range : 20Mbps to 1066Mbps per I/O) clock frequency range 
  • 4bit pre-fetch DDR architecture
  • Multiplexed, double data rate, and command/address inputs
  • 8 internal banks for concurrent operation
  • Bidirectional/differential data strobe per byte of data (DQS/DQS#)
  • Programmable Read/Write Latencies (RL/WL) and burst lengths (4, 8, or 16)
  • ZQ calibration
  • On-chip temperature sensor to control self-refresh rate
  • Partial Array Self-Refresh (PASR)
  • Deep Power-Down (DPD) mode

Block Diagram

Block Diagram - ISSI IS46LD CMOS LPDDR2 DRAMs

Datasheets

Publicado: 2025-06-02 | Actualizado: 2025-06-26