TPS23521EVM-001

Texas Instruments
595-TPS23521EVM-001
TPS23521EVM-001

Fabricante:

Descripción:
Controladores de voltaje intercambiables en caliente TPS23531 Evaluation Module for High Powe DISC-BY-MFG-7/20

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En existencias: 3

Existencias:
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Mínimo: 1   Múltiples: 1   Máxima: 5
Precio unitario:
$-.--
Precio ext.:
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Est. Tarifa:
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Precio (USD)

Cantidad Precio unitario
Precio ext.
$236.22 $236.22

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Texas Instruments
Categoría de producto: Controladores de voltaje intercambiables en caliente
RoHS:  
PCI Power Management
Programmable
72 V
36 V
1 Channel
1 mA
- 40 C
+ 125 C
SMD/SMT
Marca: Texas Instruments
Tipo de producto: Hot Swap Voltage Controllers
Serie: TPS23521-001
Cantidad de empaque de fábrica: 1
Subcategoría: PMIC - Power Management ICs
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Atributos seleccionados: 0

USHTS:
8473301180
ECCN:
EAR99

TPS23521EVM-001 Controller Evaluation Module

Texas Instruments TPS23521EVM-001 Controller Evaluation Module (EVM) contains evaluation and reference circuitry for the TPS23521. The TPS23521 is a low-side Hotswap controller with a soft start targeted at telecom applications. The Texas Instruments TPS23521EVM-001 gives a jump start for anyone designing a –48V system. It includes input clamping to support lightning surge (up to 2kV), various FET placeholders to support multiple power levels, and an output inductor to mimic any EMI filter before the DC/DC converter.

LM5060 High-Side Protection Controllers

Texas Instruments LM5060 High-Side Protection Controllers with Low Quiescent Current offers intelligent control of a high-side N-channel MOSFET during normal on/off transitions and fault conditions. The constant rise time of the output voltage results from the inrush current control. Both an Input UVLO (with hysteresis) and a programmable input OVP are provided, with an enable input offering a remote on or off control. The initial start-up VGS fault detection delay time, the transition VDS fault detection delay time, and the continuous over-current VDS fault detection delay time is programmed from a single capacitor. The MOSFET is latched off until either the enable input, or the UVLO input is toggled low and then high when a detected fault condition persists longer than the allowed fault delay time.